A semiconductor wafer is a thin, usually round slice of a semiconductor material, from which chips are made. A semiconductor wafer is processed with deposition and etching steps to produce circuits. A die is a set of semiconductor circuits on a wafer separated by scribe lines. After all of the wafer fabrication steps are completed, dies are separated, usually by sawing. The separated die units are referred to as chips.
In practice, a wafer is fabricated using standard semiconductor fabrication techniques. A silicon wafer 10 including a multiplicity of dies 12 is shown in FIG. 1. After fabrication, the wafers are put through a die sort procedure. Each individual die is electrically tested for electrical performance and circuit functioning. During a die sort procedure, the wafer is mounted on a vacuum chuck and aligned to thin electrical probes that contact each of the bonding pads on the die. The probes are connected to power supplies that test the circuit and record the results. The number, sequence and type of tests are usually directed by a computer program. Specific die sort techniques are well known to the art.
Dies which do not pass the die sort are identified. As shown in FIG. 2, the silicon wafer 10 which has gone through die sort procedures includes "passed" dies 14, which are unmarked, and "failed" dies 16, which are commonly marked with an ink dot. Alternatively, a computer map of the wafer, indicating the status of the dies, can be produced. In prior art chipmaking processes, the wafer is then cut apart, and individual "passed" chips are packaged into semiconductor devices. The packaged semiconductor devices may then be re-tested, and may be burned-in prior to final test and shipment.
The last test for a packaged semiconductor chip can be a burn-in testing. Burn-in techniques are used to identify chips that, while passing tests initially, fail very early in their operational life. The burn-in process accelerates these early failures. Burn-in testing is used generally for many commercial devices, but is usually a required process in high-reliability device lots for life-support or military applications.
Burn-in testing of semiconductor chips conventionally takes place after packaging of the semiconductor chip is completed. Prior art tests require that each individual package be separately powered while it is heated. This is generally accomplished by insertion of the packaged chip or chip set into a board socket. The board and chip are then mounted in a chamber with temperature-cycling capability, and the chip is powered (for static burn-in) or powered and exercised (for dynamic burn-in).
Difficulty has arisen with standard burn-in methodologies when multi-chip packages are manufactured. When a multi-chip package fails during burn-in, the package is opened, the failed chip is removed, and a replacement chip is inserted. The entire package must then undergo a repeat burn-in procedure. The in-use failure rate for these repaired chip packages is greater than for those in which the chips are burned in without failure and subsequent chip replacement.